1. Field
Example embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, example embodiments relate to a nonvolatile semiconductor device including a buried shield structure, and a method of manufacturing a nonvolatile semiconductor device having a buried shield structure.
2. Description of the Related Art
Semiconductor memory devices are generally used to store desired data therein and to read the stored data. The semiconductor memory devices are usually classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory device lose the stored data when an applied power is off, while the nonvolatile semiconductor memory devices maintain the stored data even though a power applied thereto is off.
A flash memory device, one of electrically erasable programmable read only memory (EEPROM) devices, has been widely employed in various electronic apparatuses such as a cellular phone, a digital camera, a portable multimedia player, a USB memory device, etc. Data may be stored into the flash memory device or may be erased from the flash memory device through a Fowler-Nordheim tunneling process or a hot electron injection process.
FIG. 1 illustrates a circuit diagram of a conventional flash memory device. Referring to FIG. 1, the conventional flash memory device 11 generally includes a row decoder 12, a memory cell array 13, a sense amplifier 14 and a source line driver (not shown).
When the flash memory device 11 is a NAND type memory device, the memory cell array 13 of the flash memory device 11 includes a plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7 and WL8, a plurality of bit lines BL1, BL2 and BLn, a plurality of string memory cells MT, and selection transistors ST1 and ST2. The string memory cells MT and the selection transistors ST1 and ST2 are electrically connected to the word lines and the bit lines.
The row decoder 12 includes the word lines WL1 to WL8 and selection gate lines SGD and SGS. The row decoder 12 further includes peripheral circuit decoders 16 and 17. The sense amplifier 14 can read data stored in a selected memory cell, and then can amplify the data of the selected memory cell. The source line driver 15 can supply source lines with a power.
The peripheral circuit decoder 17 includes high voltage transistors TR1, TR2, TR3, TR4, TR5, TR6, TR7 and TR8, whereas the memory cell array 13 has cell transistors operated with a common voltage. Since the flash memory device 11 occasionally requires a high operation voltage, the high voltage transistors and the cell transistors are simultaneously used in the flash memory device 11.
FIG. 2 illustrates a cross-sectional view of a conventional NAND type flash memory device.
Referring to FIG. 2, the NAND type flash memory device is formed on a substrate 10 having a cell transistor area A and a high voltage transistor area B. Cell transistors are provided in the cell transistor area A. Each of the cell transistors includes a first gate oxide layer 17, a first gate electrode 19, and a gate mask 21. The cell transistors are isolated by a first isolation layer 14. High voltage transistors are provided in the high voltage transistor area B. Each of the high voltage transistors includes a second gate oxide layer 18 and a second gate electrode 23. The high voltage transistors are separated by a second isolation layer 15. An insulating interlayer 24 covers the cell transistor and the high voltage transistors.
In the conventional flash memory device, electrical insulation between an isolation layer, a high voltage transistor, and a cell transistor may be easily broken when a high voltage is applied to the high voltage transistor in an operation of the flash memory device. Due to such a breakdown of electrical insulation, a punch-through leakage may be caused, thereby deteriorating electrical characteristics of the flash memory device.
Although the second isolation layer 15 shown in FIG. 2 is relatively deep in an attempt to ensure electrical insulation between the cell transistor and the high voltage transistor, processes for forming the first and the second isolation layers 14 and 15 on the substrate 10 may be considerably complicated, because the dimensions of the first isolation layer 14 are quite different from those of the second isolation layer 15. Additionally, the size of the flash memory device may be increased when the second isolation layer 15 has a large width and depth. Furthermore, the flash memory device may not properly operate in a reading operation and an erasing operation because the first and the second isolation layers 14 and 15 have considerably different dimensions.